Gabriel Lawrence

Experimenting with MiSTer Core Development: Part 1 - VGA Output

Gabriel Lawrence,   2024-09-06
  • Retro,
  • Mister,
  • Development,
  • Hardware,
  • FPGA

    • The MiSTer project offers a powerful FPGA platform for recreating and exploring classic computer and gaming systems. As someone deeply interested in retro computing and hardware design, I’ve decided to take on the challenge of creating my own MiSTer core, inspired by Ben Eater’s 6502 breadboard computer and my own experiments with real hardware. However, before diving into the complexities of building a full 6502 computer, I want to start with something more fundamental—building a simple VGA output.

    The goal is to gain hands-on experience with MiSTer core development by experimenting with VGA signal generation. VGA is one of the most critical aspects of generating visual output on a retro computer. By first understanding how video signals work and successfully generating them on the MiSTer platform, I’ll lay the foundation for future steps, such as integrating a 6502 CPU, memory, and peripherals.

    Cloning the MiSTer Template Project and Creating Your Own Core

    One of the advantages of developing for MiSTer is the availability of template projects that provide a solid foundation for building custom cores. By cloning the MiSTer template project, you can get started quickly and focus on the unique aspects of your core without having to reinvent the wheel. Below, we’ll walk through the steps to clone the template project, set it up in your development environment, and modify it to create a new MiSTer core.

    To begin, you’ll need to clone the MiSTer template project from GitHub. This template includes all the necessary files and configurations for basic core functionality, such as handling input/output, video, and communication with the MiSTer framework. Here's how to clone the template repository:

    git clone https://github.com/MiSTer-devel/Template_MiSTer.git

    The template project includes:

    • A rtl folder for Verilog code.
    • A sys folder for configuration files and platform-specific scripts.
    • Basic support for video output (VGA/HDMI), input devices, and MiSTer’s Hard Processor System (HPS).

    A good first step is to compile the template project and confirm that it builds successfully, and you can run it on your MiSTer.

    Compile and Test the Template Core

    To compile the project using Intel’s Quartus Prime Lite, follow these steps:

    • Open Quartus and load the .qpf file for the template core (e.g., Template.qpf).
    • Ensure that the correct FPGA device is selected (Cyclone V for the DE10-Nano).
    • Start the compilation process by selecting "Start Compilation" from the Processing menu or pressing Ctrl+L.

    Once the compilation is complete, Quartus will generate an .rbf file, which is the bitstream that MiSTer uses to configure the FPGA.

    Deploy the Template Core to MiSTer

    To test your newly compiled core, copy the .rbf file to your MiSTer system. You can do this by:

    • Using SCP to upload the file to your MiSTer device over the network:
    scp output_files/Template.rbf root@MiSTer_IP:/media/fat
    • Or by manually copying the file to your MiSTer’s SD card.

    Once the file is on your MiSTer, load it from the MiSTer menu and test the VGA output. If everything works correctly, you should see the TV snow pattern, which is the default output of the template project.

    Renaming the Project

    Before making any modifications to the code, it's a good idea to rename the project files and directories to reflect the name of your new core. This involves updating references within files like the .qpf and .qsf project files (used by Quartus) and renaming the files themselves.

    Here’s how you can proceed:

    • Move or rename any file starting with "Template" to your chosen core name.
    • Open the .qpf file in a text editor and update the project name to reflect the new core.
    • Update the .qsf and .qip files as well, ensuring that they reference the appropriate project files and directories.

    Creating a VGA Core

    VGA, or Video Graphics Array, is a widely used video display standard that was introduced in the late 1980s. It transmits analog signals for red, green, and blue (RGB) color channels, along with horizontal and vertical sync signals that control the display's timing. Despite being replaced by more advanced interfaces, VGA remains crucial in retro computing, hardware development, and educational projects, providing a fundamental understanding of video signal processing.

    Basics of VGA Timing and Signal Generation

    At the core of VGA is the transmission of signals that display images line by line. This happens at such a fast rate that the human eye perceives it as a continuous image. A VGA signal consists of three primary components:

    • RGB Signals: Red, green, and blue color values for each pixel.
    • HSYNC (Horizontal Sync): Marks the end of one line and the beginning of the next.
    • VSYNC (Vertical Sync): Marks the end of one frame and the start of the next.

    VGA 640x480@60Hz Timing Specifications

    To generate a proper VGA signal, we need to manage the timing of various components accurately:

    • Pixel Frequency: 25.175 MHz
    • Horizontal Timing: 800 total columns (640 visible, 16 front porch, 96 sync pulse, 48 back porch)
    • Vertical Timing: 525 total rows (480 visible, 10 front porch, 2 sync pulse, 33 back porch)

    Code to Generate a VGA Image

    The GL_VGA module generates VGA signals based on the pixel clock and the horizontal (hc) and vertical (vc) counters. These counters track the position of the pixel being drawn on the screen, and the module updates the RGB values and sync signals accordingly.

    1. Horizontal and Vertical Counters

    The horizontal and vertical counters (hc and vc) track the pixel position. They increment with each clock cycle, resetting when they reach the end of a line or frame. This allows the module to determine exactly where it is in the drawing process.

    • Horizontal Counter (hc): Tracks the current pixel within a line. When it reaches 800 columns, it resets, and the vertical counter increments.
    • Vertical Counter (vc): Tracks the current line being drawn. Once it reaches 525 rows, it resets, marking the end of a frame.
    2. Sync Signals

    The horizontal sync (HSYNC) and vertical sync (VSYNC) signals are generated based on the counters and timing parameters (front porch, sync pulse, back porch). These signals ensure the monitor knows when to move to the next line or frame.

    • HSYNC: Asserts during the horizontal sync pulse, telling the monitor to move to the next line.
    • VSYNC: Asserts during the vertical sync pulse, signaling the end of a frame.
    3. Generating the VGA Pattern

    The RGB signals (vr, vg, and vb) control the color of each pixel. In this module, we generate a simple test pattern of vertical and horizontal bars. The colors are determined by the horizontal and vertical counters.

    • Red Bars: Red is turned on when the horizontal counter reaches certain values, creating vertical red bars every 8 pixels.
    • Blue Bars: Blue is toggled on and off based on the vertical counter, creating horizontal blue bars.

    This pattern produces alternating red and blue bars across the screen, with additional logic to create a white border around specific columns and rows.

    You can explore the full project here: GLVGA_MiSTer.